Currently pursuing
M.S. in Biomedical Engineering
The George Washington University
3.7 G.P.A
Candidate May 2019
Undergratuate Courses Taken:
PROJECTS COMPLETED
Amplifier Project
I built a cascading amplifier composed of two stages; the common emitter stage and the common collector stage. The small input signal from the function generator outputs a large voltage across the load, thus amplifying the signal.
I set up a Cascaded Amplifier to amplify the small input voltage from the function generator. Essentially I took a 350mV signal input and produced an output of about 8.94V going through the 8Ω load which in this case is a speaker. This peak voltage is derived from the Power Formula: P= (V^2)/R. In doing so I had two amplifiers cascaded together; the Common Emitter Amplifier and the Common Collector Amplifier. Due to the fact that there was too large of a current to run through a typical common collector amplifier, the common collector stage was replaced for what is called the Darlington Class AB setup. In this setup I placed three diodes in series with each other to ensure that the Bipolar Junction Transmitters stayed on at all times. The gain (VO/VI) for the common emitter portion needed to be about 25 and the gain for the common collector was expected to be 1. The gain of 25.56 came from the expected output voltage swing of 8.94V divided by the input voltage of 350mV. The VCC (DC Voltage) came from the DC power supply and this was set to 12V and -12V along the rails. Also the capacitor values were high. This allowed there to be very low impedance to current which symbolized the shorting of capacitors when dealing with AC Voltage. The input and output impedances for the common emitter were both medium value while for the common collector, the input impedance was high and the output impedance low.
Project 2: Designed a 2 bit Arithmetic Logic Unit in Verilog
The goal of this project was to build a 2-bit Arithmetic Logic Unit in Verilog. The code was expected to carry out a variety of different specifications. The first operation was the left shift operation. This operation shifts any binary number “1” one bit to the left with a possible carry value if the binary number 1 is at the last bit to the left. For example, 001-> 010->100-> next the binary numbers would be 000 with a carry of 1. In the next operation, the opposite takes place. Here, the binary number “1” is shifted one bit to the right. In the third operation addition takes place. This adds the binary numbers. For example:
A1A0
+B1B0
C1C0
The next operation represents the subtraction of binary numbers. The subtraction operation functions similarly. The B bits are subtracted from the A bits. If there is case where the A bit is less than B bit, then the carry output must be triggered. For example:
Carry-> 1 0
1
However, if the A bit is larger than the B bit, then the bits are subtracted from one another. This is explained later in the coding process.
The last four operations are the XOR function, OR function, AND function, and the set function where the carry output is 1 and the sum output is 1.
Project 3: Built an ECG Simulation
A differential amplifier circuit was designed for this experiment. The resistor values were found using the Gain equation. The first stage of this circuit involved two Op-Amps. The input of the first Op-Amp was 10mV and the input of the second was 5mV. The difference between these Op-Amps created a 5mV input signal that was amplified to a higher voltage creating a gain within the range of 500-1000. This voltage passed through the third Op-Amp with a gain of 1. This output waveform was passed through the DAQ Hardware to convert the analogue signal to a digital one, creating samples of the continuous waveform. The ECG signal was generated in LabView and the MatLab script was used to determine the RR intervals. Upon finding these peak values, the BPM for the heart was determined.
Project 4: I used C Programming to simulate Facebook using a series of Binary Search Trees.